High-voltage metal-oxide-semiconductor (HVMOS) devices are widely used in many electrical applications, such as CPU power supplies, power management systems, AC/DC converters, etc.
FIG. 1 illustrates a conventional n-type HVMOS (HVNMOS) device 2 formed over substrate 16. HVNMOS device 2 includes gate electrode 4, drain region 6 in high-voltage n-well (HVNW) 8, and source region 10 in high-voltage p-well (HVPW) 12. Shallow trench isolation (STI) region 5 spaces drain region 6 and gate electrode 4 apart, so that high drain-gate voltages can be applied. HVNMOS device 2 is formed on an n-type buried layer (NBL) 14, which is further formed on p-type substrate 16.
The conventional HVNMOS device 2 suffers drawbacks when used in certain applications. For example, power IC or driver IC may be involved with negative voltages. Therefore, when used in power IC or driver IC, HVNMOS device 2 may have negative source-to-substrate voltages and/or negative drain-to-substrate voltages. In such a case, a forward bias is applied on diode 18, which is formed of p-type substrate 16 and n-type NBL 14. The n-type NBL 14 is further connected to n-type HVNW region 8 and N+ drain region 6. Therefore, diode 18 will be turned on by negative drain-to-substrate voltages. This adversely causes the increase in leakage current, and possibly the reduction in breakdown voltage of HVNMOS device 2.
What is needed in the art, therefore, is a HVMOS device with good performance when positive source-to-substrate and drain-to-substrate voltages are applied, and is also capable of performing well for negative source-to-substrate and drain-to-substrate voltages.